PSL Assertion Checking with Temporally Extended High-Level Decision Diagrams

The paper proposes a novel method for PSL language assertions conversion to a system representation model called High-Level Decision Diagrams (HLDD). Previous works have shown that HLDDs are an efficient model for simulation and convenient for diagnosis and debug. We present a technique, where checking of PSL assertions is integrated into fast HLDDbased simulation. There are three main contributions in the paper. The first one is a methodology for direct conversion of PSL properties to HLDD. The second one is a temporal extension for the existing HLDD model. The third one is HLDD-based simulator modification to support the new type of HLDDs and assertions checking. Index Terms dynamic verification, assertions, property specification language (PSL), high-level decision diagrams